1. Field of the Invention
This invention relates generally to the field of circuits used to synchronize the energizing of various parts of an extended circuit. A circuit such as that of this invention is characterized as a "power-up circuit," and serves to delay the application of electrical power at power-up until the level of voltage available to the extended circuit is sufficiently high to ensure that all parts of that extended circuit can operate properly. More particularly, the circuit of the present invention can serve to delay the application of power to the output pull-up and pull-down stages in output buffers until those stages can be controlled by the rest of the output buffer and associated circuitry. More particularly yet, the present invention can provide a means of delaying circuit activation until the rising power-supply-voltage is sufficiently high to ensure that the output buffer is placed in a definite state before its pull-up and pull-down stages are energized. Yet more particularly, the present invention--using a combination of MOSFET and bipolar transistor circuitry--introduces a hysteresis into the energizing/de-energizing process such that the turn-on-threshold-voltage marking the point at which the power-supply-voltage is applied to the extended circuit as the power supply voltage is rising is significantly higher than the turn-off-threshold-voltage marking the point at which the power-supply-voltage is removed from the extended circuit as the power-supply-voltage is falling. This permits a relatively high turn-on-threshold-voltage to be set, without a concern that the circuit will be de-energized by normal fluctuations in the applied power supply voltage.
Another sub-field in which the circuit of the present invention can be categorized is that of reset circuits, i.e., circuits used to set to logic-low the levels of a group of logic stages in an extended circuit or, more generally, to set the levels of the logic stages to definite values, logic-low or logic-high.
2. Description of the Prior Art
In general, power is supplied to an extended logic circuit by a power supply connected across the circuit. This generally is accomplished by connecting the low-potential power rail of the logic circuit to ground and connecting the high-potential power rail to the high side of the power supply, the low side of which is grounded. (The high-potential power rail voltage for which the circuit is designed to operate is usually referred to as V.sub.CC, and the voltage on the low-potential power rail as GND.) Normally the power supply is part of the circuitry and when ac power is provided to the power supply input the dc output voltage of that power supply--V.sub.ps --will not instantaneously rise to the full design voltage for the high-potential power rail of the logic circuit. Rather, the power-supply-voltage V.sub.ps will commence at ground level and ramp up more or less linearly to the design voltage over a interval on the order of milliseconds. Problems arise because parts of the extended logic circuit will become active long before V.sub.ps brings the high-potential power rail up to the level where the entire circuit is operating properly. This can result in various stages being placed in indeterminate states rather than in one of the two well-defined binary states: logic-high and logic-low. This in turn can result in excess power dissipation both within the circuit and from the common bus to which the circuit is ultimately coupled.
In general, each of a plurality of logic circuits will be coupled to a common bus through a three-state output buffer, with provision for ensuring that at most one of the output buffers is active at a time. This is done through an output enable gate. There will be an output enable gate signal for each of the buffers. The problem during power-up is that bipolar logic outputs start conducting before the voltage on the high-potential power rail reaches the level necessary for an effective disenabling signal to be sent to the output enable gate. The consequence is that one or more (or even all) of the output buffers may be active (enabled) during this interval, with their outputs either current-sinking or current-sourcing. In the alternative, those buffers may be both current-sourcing and current-sinking, a most undesirable situation from a power dissipation perspective, where the high-potential power rail is coupled to the low-potential power rail through the output stages of one or more of the output buffers.
The usual approach in solving this problem is to couple to each output buffer a power-up circuit that will generate at an early stage in the ramping up of V.sub.ps a signal to hold the output buffer in its inactive state (that is, the "high-Z state" or simply "Z state"). The power-up circuit is a "fix" added to the main circuit to make up for the fact that the main circuit cannot generate a disabling signal--or simply a signal designed to ensure that all stages are in a definite logic state--soon enough. A power-up circuit is intended to generate an output voltage V.sub.PU which is in a definite logic state by the time that V.sub.ps reaches the level at which any of the logic outputs start conducting. That definite-logic-state signal can then be used to ensure that the output logic buffer is disabled, when the power-up circuit is used in connection with a three-state output buffer tied to a common bus. A generic array of such a buffer/bus circuit incorporating a power-up circuit is depicted in FIG. 1, which shows the output enable gate (OEG) to be an OR gate with one input from the power-up circuit and the other from that part of the circuit that generates the output enabling signal once the circuit is in operation, i.e., once the voltage on the high-potential power rail is at operative levels. With this particular layout, it can be seen that as long as the power-up output V.sub.PU is logic-low the OEG will send a disabling signal to the output buffer ensuring that that buffer presents a high-Z appearance to the common bus. During power-up, therefore, the power-up circuit must output a voltage V.sub.PU that is logic-high throughout the values of V.sub.ps for which the logic circuits can conduct, but a definite-state disabling signal nOE cannot be generated. For transistor-transistor logic (TTL)--i.e., bipolar logic--this will be the range from about 2 V.sub.BE to 4 V.sub.BE, with V.sub.BE being defined as the voltage drop across the base and emitter nodes of a bipolar transistor. Thus the requirement is that the power-up circuit must output a logic-high signal during ramp-up as V.sub.ps is varying from 2 V.sub.BE to 4 V.sub.BE, and that it then be locked at logic low so as to return control of the buffer to nOE.
Early power-up circuits are described in Houk et al. (U.S. Pat. No. 4,481,430, issued 1984) and in Krantz (U.S. Pat. No. 5,051,611, issued in 1991). The basic circuit of Houk is shown in FIG. 2 (Prior Art). It can be seen that as V.sub.ps ramps up from ground, the power-up output voltage V.sub.PU will first follow V.sub.ps, since there will be no current through resistor R3 and hence no voltage drop across that resistor. That is, transistor Q1 will be non-conducting until V.sub.ps, is high enough to cause forward conduction through diocies D1 and D2 and provide base drive to Q1. Q1 will not conduct until the drop across R2 equals V.sub.BE, the voltage required across the base-emitter junction of Q1 to turn on the transistor. The "forward" base-emitter voltage drop will be taken to be the same across all transistors, and also to be the forward-conduction voltage drop for all the circuit diodes (which are generally bipolar transistors themselves with the collector and base nodes tied together). Thus it can be seen that Q1 will turn on when V.sub.ps reaches a voltage [3+R1/R2]V.sub.BE, or about 4 V.sub.BE when the R1 and R2 resistors are comparable to one another. When Q1 turns on the output of the power-up circuit will fall to V.sub.sat (the collector-emitter drop across a conducting bipolar transistor of the circuit) and will remain there as long as V.sub.ps remains above [3+R1/R2]V.sub.BE. For this duration, V.sub.PU will be locked at logic-low. The gate to which V.sub.PU is connected-generally an OR gate as shown in FIG. 1--is wired so that a logic-low V.sub.PU does not have any effect on the state of the output buffer. It can be seen, then, that for V.sub.ps &gt;[3+R1/R2]V.sub.BE the power-up circuit cuts out (cedes control of the buffer). As is shown in Houk et al., the output of their power-up circuit is connected to an OEG in such a way that when V.sub.PU exceeds about 2 V.sub.BE the output of the OEG will be logic-low, regardless of the nOE signal. Thus, the presence of the power-up circuit of Houk et al. ensures that the output buffer is disabled for 2 V.sub.BE &lt;V.sub.ps &lt;4 V.sub.BE. The power-supply-voltage at which the power-up circuit yields control, 4 V.sub.BE in this prior-art circuit, is the ramp-up threshold. Because of the design of the power-up circuit of Houk et al., as shown in FIG. 2, it can be seen that as the V.sub.ps voltage drops below the ramp-up threshold--because of powering down of the circuit or because of fluctuations in the power-supply-voltage--transistor Q1 will turn off and the power-up circuit will re-assert control, disabling the buffer. Note in particular that with the prior-art circuit of FIG. 2, this will occur at the same voltage as that of the power-up threshold, i.e., at 4 V.sub.BE if R1=R2. This is undesirable, because once the buffers and their peripheral circuits are powered up, they can tolerate high-potential power rail voltages considerably below what they can tolerate during power-up. Because of this it is desirable to be able to introduce a certain hysteresis in the power-up circuit operation, a hysteresis whereby the turn-on threshold is higher than the turn-off threshold. In this way the circuit--and the bus to which it is coupled--can be safeguarded during power up and also safeguarded against unnecessary shut-downs when V.sub.ps voltage falls below the power-up threshold because of load-, noise, and/or temperature-induced fluctuations not incompatible with proper functioning of the circuit.
The circuit of Kantz addresses the susceptibility of earlier power-up circuits to cause unwanted shut downs due to fluctuations in the high-potential power rail voltage. It does this by introducing a hysteresis such that, once the power-up circuit has relinquished control over the extended circuit--at the V.sub.ps up-threshold V.sub.UTh --it will not reassert that control until V.sub.ps has fallen below a different threshold, the down-threshold V.sub.DTh, where V.sub.DTh &lt;V.sub.UTh. FIG. 3 depicts the essence of the power-up circuit of Kantz. As V.sub.ps increases from ground potential the diode stack is at first not conducting; transistor Q3 receives no base drive and hence is `off.` The output voltage of the power-up circuit is equal to V.sub.ps during this interval. Once V.sub.ps exceeds V.sub.BE, transistor Q2 turns on. However, the output voltage V.sub.PU continues to track V.sub.ps, since Q3 remains off and the base current through Q2 will result in negligible voltage drop across resistor R7. There will, however, be current through R4, and a corresponding voltage drop across R4. Initially, this current all passes through Q2. When V.sub.ps reaches a certain voltage, however, the diode stack consisting of D3 and D4 will start conducting and the current through R4 will then be the sum of the respective currents through the diode stack branch and through Q2. As V.sub.ps continues to increase, it will pass the threshold V.sub.UTh at which base drive is supplied to Q3; at this point, V.sub.PU will drop to V.sub.SAT and constitute a logic-low signal which through other circuitry, will yield control over the output buffer. This also will result in Q2 turning off for lack of base drive. (This turning-off of Q2 is essential to the hysteresis effect in Kantz.) During the period after this power-up circuit has yielded control, all of the current through R4 passes through the diode stack. Consequently, when V.sub.ps decreases--either during power-down or during a transitory fluctuation--it falls off to a voltage V.sub.DTh lower than V.sub.UTh before the base voltage of Q3 falls below V.sub.BE causing Q3 to turn off and hence the power-up circuit to reassert control and shut the output buffer down. Because Kantz allows the power-up threshold voltage V.sub.UTh to be set higher than the power-down threshold voltage V.sub.DTh, it permits V.sub.UTh to be set higher than would be desirable when one has to select a single threshold which is to be a compromise between (1) providing adequate protection during power-up and (2) avoiding shutdowns for minor fluctuations in the power supply voltage.
Although the power-up circuit of Kantz allows separation of the threshold voltages V.sub.UTh and V.sub.DTh, it is limited with regard to the fixing of the values of those threshold voltages by means other than selection of alternative resistance values. This is of particular concern given the types of variations observed in semiconductor-fabricated resistors, wherein resistance values as manufactured can be off from the design values by as much as 30%. Any alternative means used to change V.sub.UTh and V.sub.DTh, such as by adding supplemental diode means to the circuit branch including transistor Q2 could bring the power-up circuit outside the range of acceptable operating conditions, particularly as required power supply levels are reduced. More fundamentally. Kantz is limited to TTL (bipolar) technology and is not adaptable for use in the more recent integrated circuitry utilizing both bipolar and MOSFET technology and designated as BiCMOS. Finally, it must be emphasized that none of the known prior-art circuits assert control until the power-supply-voltage is on the order of 2 V.sub.BE. This can be a problem with many modern circuit stages, which may become active somewhat below 2 V.sub.BE.
Therefore, what is needed is a BiCMOS power-up circuit having unequal threshold turn-on/turn-off characteristics wherein turn-on occurs at a higher threshold than turnoff and where the two thresholds can be adjusted independently of one another. In particular, what is needed is such a power-up circuit capable of asserting control at an up-threshold voltage clearly below 2 V.sub.BE.